1. Field of the Invention
The present invention generally relates to a method of descrambling scrambled data using a scramble pattern. More particularly, this invention relates to a method of descrambling scrambled data recorded on a recording medium in a disk apparatus, and a circuit for generating a scramble pattern.
2. Description of the Related Art
Since digital video disk (DVD) media promises large-capacity, individual makers are trying to develop DVD systems. Recently, enthusiastic efforts have been, and are being, made to standardize the DVD specifications.
FIG. 1 presents a flow diagram showing a data demodulating process in a DVD drive designed exclusively to read data. A disk 100 has data recording tracks arranged in a spiral form. Physical sector data is recorded on each track in a sector by sector manner. Physical sector data read from the disk 100 is subjected to EFM (Eight to Fourteen Modulation) Plus demodulation to yield recorded sector data 101. The recorded sector data 101 includes plural pieces of sector data 102, plural pieces of first error correction code (ECC) data PI affixed to the individual row data in the sector data 102, and plural pieces of second error correction code data PO affixed to the individual column data in the sector data 102. The data are recorded on the disk 100 in the order of the sector data 102, the first error correction codes PI and the second error correction codes PO.
Sixteen pieces of sector data 102, sixteen first error correction codes PI and sixteen second error correction codes PO are grouped in the recording order, thus yielding ECC-affixed data 103. Sixteen pieces of sector data 102 form one block.
Error correction is performed on one block of sector data 102 using the first error correction codes PI. Then, error correction is performed on one block of sector data 102 using the second error correction codes PO. In this manner, sixteen pieces of scrambled data 104 are generated. Each scrambled data 104 is data generated by performing an exclusive OR operation on the original data and a scramble pattern.
To generate sixteen pieces of original sector data 105, an exclusive OR operation on each scrambled data 104 and a scramble pattern used for the generation of each scrambled data 104, or descrambling, is executed.
As shown in FIG. 2, sector data 105 includes main data of 2048 (2K) bytes, 4-byte identification data ID, a 2-byte error correction code IEC for the identification data ID and a 6-byte reserve area RSV, all of the latter three being affixed to the front portion of the main data. The sector data 105 further includes a 4-byte error correction code EDC, which is affixed to the end portion of the main data to detect an error in the main data. The identification data ID includes a 1-byte sector information field and a 3-byte sector number field.
FIG. 3 shows a conventional scramble pattern generator 110 which is used to descramble scrambled data. The scramble pattern generator 110 includes a feedback type shift register 111 of fifteen bits b14 to b0, and an exclusive OR (EOR) gate 112.
The EOR gate 112 receives the logic values of the bits b14 and b10 and performs an exclusive OR operation thereon. The resultant logic value is supplied to the bit b0. The shift register 111 receives an initial scramble pattern in response to the first pulse of a clock CK. The shift register 111 further successively shifts the logic values of the bits b13-b0 to the adjoining bits b14-b1, respectively, every time each pulse of the clock CK is input. The shift register 111 receives the output logic value of the EOR gate 112 at its bit b0 and outputs the logic values of the bits b7-b0 as an 8-bit scramble value SK for every eight pulses of the clock CK.
As shown in FIG. 4, the initial value of a scramble pattern is determined by the ID value of the bits b7-b4, which is assigned to the sector number field of the identification data ID. That is, one initial pattern is assigned to one block formed by sixteen data sectors. When the ID value "0(h)" ((h): a hexadecimal notation) of the bits b7-b4 is assigned to the sector number field, for example, in the first block, the initial scramble pattern "0001(h)" is determined. At this time, 00000000000001(2) ((2): a binary notation) is set in the bits b14-b0 of the shift register 111. Accordingly, the logic value 00000001(2) of the bits b7-b0 is output as the initial 8-bit scramble value SK from the shift register 111.
An exclusive OR operation on the initial 8-bit scramble value SK and the first 8-bit main data of the scrambled data 104 is performed to generate 1-byte original data. The next 1-byte main data is descrambled using 8-bit scramble value SK outputted from the shift register 111 after receiving eight pulses of the clock CK.
Since the conventional scramble pattern generator 110 acquires an 8-bit scramble value SK from the shift register 111 in accordance with the transfer rate of main data, it requires the clock CK, the frequency of which is eight times the transfer rate of main data. When the transfer rate of main data is set to 10 Mbytes/sec, for example, the scramble pattern generator 110 needs a clock CK that has a frequency of 80 megahertz (MHz). The high frequency of the clock CK stands in the way of improving the transfer rate of main data and fast data processing.
The last data of the data sector 105, or the 2048th data, is descrambled by using an 8-bit scramble pattern, which has been generated by the input of 2047.times.8 clock pulses to the shift register 111. In other words, the 2048th data is acquired only after 2047.times.8 clock pulses are input to the shift register 111. Furthermore, when the shift register 111 inputs 1023.times.8 clock pulses, descrambling 1024-byte data is obtained using a corresponding 8-bit scramble pattern. It is therefore not possible to acquire the desired original byte data immediately after the descrambling operation is initiated. This obstructs fast data processing.